When designing synchronous digital circuits, logic functions are implemented and connected together to form a complete and functioning design. The precise timing of events in synchronous digital circuits is controlled by so-called clock signals. The task of the clock signals is to reduce the uncertainty in delay between sending and receiving storage elements. Storage elements such as latches and flip-flops, respond to a predefined characteristic of a clock signal (e.g., a leading and/or trailing edge of the clock signal) by sampling output signals supplied by combinational logic or other storage elements. The sampled value is internally preserved by the storage element as the state of the circuit. The state of the storage element is made available for new computations after a certain delay. These storage elements are also referred to as clocked devices because they are responsive to clock signals in order to alter their state.
Synchronization requires that data arrive at a clocked device, such as a flip-flop, at an appropriate time relative to a clock signal pulse. There is a specified “setup time” and “hold time” for any clocked device. Setup time requires that input data must be present at the data input lead of clocked device and be in stable form for a predetermined amount of time before the clock signal transition (rising or falling edge of the clock signal). Hold time requires that, for proper operation, the data be stable from the time of the clock signal transition up to a certain time interval after the clock signal transition. When implementing a circuit containing thousands of clocked devices, any violation of the stringent hold time or setup time parameters would prevent proper operation of the implemented circuit. A key process in implementing a logic circuit is to synchronize the setup and hold time of data with the arrival of a corresponding clock signal.
Commonly, setup time violations can be remedied by slowing down the speed at which the design is clocked. A deficiency of such an approach is that the maximum frequency of the clock, and hence the performance of the overall circuit, is dictated by the slowest stage of logic through the circuit.
Hold time violations, however, typically persist regardless of the speed of the clock signal and depend on the clock skew in various parts of the circuit design. As a clock signal traverses different branches of a tree-like distribution network, its critical component (e.g., a leading clock edge) may arrive at different storage elements at different times. This timing difference between clock arrival times at different points in the digital circuit is called clock skew. Clock skew may be attributed to, for example, component elements not being perfectly matched throughout the chip or to a drop in the power supply at one location of the chip and not at another, which would cause a difference in delay in signal propagation. Therefore, in implementing a circuit, the proper timing of clock signals may be hindered due to excessive delay in the clock signal distribution paths by reason of clock skew.
Regardless of the reason for the presence of clock skew, the effect on the functionality of an integrated circuit is significant. Clock skew may cause data in a first clocked device to shift earlier than data in a second subsequent clocked device. The hold time requirement of the second clocked device is violated and data bits may then be lost. This situation is commonly referred to as a “race condition”.
Current design tools for integrated circuits do not accurately model the phenomenon of clock skew since the latter is due in part to the physical properties of the material with which the integrated circuit is built. Moreover, the physical properties of the manufactured material may vary from one integrated circuit to the other. As a result, producing an accurate model for all integrated circuits is prohibitively complex if not impossible. When hold-time violations occur post-fabrication of an integrated circuit design, it may only affect a portion of the total manufactured devices causing them to be non-functional. This results in either a lower yield of the manufacturing process or the integrated circuit must be redesigned and rebuilt to account for clock skew. A lower yield results in a higher cost of obtaining functional devices, while the redesigning and rebuilding process often results in significant delays in launching a new integrated circuit on the market. Both lower yield and/or redesign result in lost revenues and in an increase in manufacturing costs.
A current approach to overcome the problem of hold time violations is to purposefully introduce delays in the integrated circuit to compensate for potential foreseen hold time violations. This introduction of delays can have a significant impact on the performance of the resulting integrated circuit, in particular if a very conservative approach is used and more delays then strictly required are included in the integrated circuit. However, if insufficient delays are introduced with the goal of improving performance, hold time violations may remain in the circuit post-fabrication and the result is a non-functional integrated circuit due in part to the presence of race conditions.
Another deficiency with currently used approaches is that they provide no suitable solutions for addressing the presence of hold time violations post-fabrication.
Another deficiency associated with circuits in which the components operate in accordance with a common global clock is that there are sudden surges in power consumption each time a clock transition causes a change of state in the clocked components. Consequently, power sources powerful enough to supply power during these sudden surges must be used to operate devices making use of such circuits even though the average power consumption of the circuit may be significantly less.
In light of the above, it appears that there is a need in the industry for providing a clock propagation circuit and a method for propagating clock signals that alleviate at least in part the deficiencies of the prior art.